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at28hc64b 64k (8k x 8) high speed cmos e 2 prom with page write and software data protection features fast read access time - 55 ns automatic page write operation internal address and data latches for 64-bytes fast write cycle times page write cycle time: 10 ms maximum 1 to 64-byte page write operation low power dissipation 40 ma active current 100 m a cmos standby current hardware and software data protection data polling and toggle bit for end of write detection high reliability cmos technology endurance: 100,000 cycles data retention: 10 years single 5v 10% supply cmos and ttl compatible inputs and outputs jedec approved byte-wide pinout commercial and industrial temperature ranges note: plcc package pins 1 and 17 are dont connect. pdip, soic top view plcc top view pin name function a0 - a12 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc dont connect pin configurations tsop top view description the at28hc64b is a high-performance electrically erasable and programmable read only memory (eeprom). its 64k of memory is organized as 8,192 words by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 55 ns with power dissipation of just 220 mw. when the device is deselected, the cmos standby current is less than 100 m a. the at28hc64b is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 64-byte page register to allow (continued) 0274d at28hc64b 2-267
block diagram writing of up to 64-bytes simultaneously. during a write cy- cle, the addresses and 1 to 64-bytes of data are internally latched, freeing the address and data bus for other opera- tions. following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected, a new access for a read or write can begin. atmels at28hc64b has additional features to ensure high quality and manufacturability. the device utilizes in- ternal error correction for extended endurance and im- proved data retention. an optional software data protec- tion mechanism is available to guard against inadvertent writes. the device also includes an extra 64-bytes of eeprom for device identification or tracking. description (continued) temperature under bias................. -55c to +125c storage temperature...................... -65c to +150c all input voltages (including nc pins) with respect to ground ................... -0.6v to +6.25v all output voltages with respect to ground .............-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ................... -0.6v to +13.5v *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* 2-268 at28hc64b
device operation read: the at28hc64b is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high- impedance state when either ce or oe is high. this dual line control gives designers flexibility in preventing bus contention in their systems. byte write: a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cy- cle. the address is latched on the falling edge of ce or we, whichever occurs last. the data is latched by the first rising edge of ce or we. once a byte write has been started, it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectively be a poll- ing operation. page write: the page write operation of the at28hc64b allows 1 to 64-bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; after the first byte is written, it can then be fol- lowed by 1 to 63 additional bytes. each successive byte must be loaded within 150 m s (t blc ) of the previous byte. if the t blc limit is exceeded, the at28hc64b will cease accepting data and commence the internal programming operation. all bytes during a page write operation must re- side on the same page as defined by the state of the a6 to a12 inputs. for each we high to low transition during the page write operation, a6 to a12 must be the same. the a0 to a5 inputs specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnec- essary cycling of other bytes within the page does not oc- cur. data polling: the at28hc64b features data poll- ing to indicate the end of a write cycle. during a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be pre- sented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at any time during the write cycle. toggle bit: in addition to data polling, the at28hc64b provides another method for determining the end of a write cycle. during the write operation, succes- sive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop toggling, and valid data will be read. toggle bit reading may begin at any time during the write cycle. data protection: if precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. hardware data protection: hardware features protect against inadvertent writes to the at28hc64b in the following ways: (a) v cc sense - if v cc is below 3.8v (typical), the write function is inhibited; (b) v cc power-on delay - once v cc has reached 3.8v, the device will auto- matically time out 5 ms (typical) before allowing a write; (c) write inhibit - holding any one of oe low, ce high or we high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. software data protection: a software-control- led data protection feature has been implemented on the at28hc64b. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28hc64b is shipped from atmel with sdp disabled. sdp is enabled by the user issuing a series of three write commands in which three specific bytes of data are written to three specific addresses (refer to the software data protection algorithm diagram in this data sheet). after writ- ing the 3-byte command sequence and waiting t wc , the entire at28hc64b will be protected against inadvertent writes. it should be noted that even after sdp is enabled, the user may still perform a byte or page write to the at28hc64b. this is done by preceding the data to be written by the same 3-byte command sequence used to enable sdp. once set, sdp remains active unless the disable com- mand sequence is issued. power transitions do not dis- able sdp, and sdp protects the at28hc64b during power-up and power-down conditions. all command se- quences must conform to the page write timing specifica- tions. the data in the enable and disable command se- quences is not actually written into the device; their ad- dresses may still be written with user data in either a byte or page write operation. after setting sdp, any attempt to write to the device with- out the 3-byte command sequence will start the internal write timers. no data will be written to the device, however. for the duration of t wc , read operations will effectively be polling operations. (continued) at28hc64b 2-269
symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1v com., ind. 100 (1) m a i sb2 v cc standby current ttl ce = 2.0v to v cc + 1v 2 (1) ma i cc v cc active current f = 5 mhz; i out = 0 ma 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma .40 v v oh output high voltage i oh = -400 m a 2.4 v note: 1. i sb1 and i sb2 for the 55 ns part is 40 ma maximum. dc characteristics at28hc64b-55 at28hc64b-70 at28hc64b-90 at28hc64b-120 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% dc and ac operating range mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z chip erase v il v h (3) v il high z notes: 1. x can be v il or v ih . 2. refer to the ac write waveforms diagrams in this data sheet. operating modes 3. v h = 12.0v 0.5v. device identification: an extra 64-bytes of eeprom memory are available to the user for device identification. by raising a9 to 12v 0.5v and using ad- dress locations 1fc0h to 1fffh, the additional bytes may be written to or read from in the same manner as the regular memory array. device operation (continued) 2-270 at28hc64b
at28hc64b-55 at28hc64b-70 at28hc64b-90 at28hc64b-120 symbol parameter min max min max min max min max units t acc address to output delay 55 70 90 120 ns t ce (1) ce to output delay 55 70 90 120 ns t oe (2) oe to output delay 0 30 0 35 0 40 0 50 ns t df (3, 4) oe to output float 0 30 0 35 0 40 0 50 ns t oh output hold 0 0 0 0 ns ac read characteristics notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce, whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read waveforms (1, 2, 3, 4) t r , t f < 5ns input test waveforms and measurement level output test load typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v pin capacitance (f = 1 mhz, t = 25c) (1) note: 1. this parameter is characterized and is not 100% tested. at28hc64b 2-271
symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width ( we or ce) 100 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns ac write characteristics ac write waveforms we controlled ce controlled 2-272 at28hc64b
symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 m s t wph write pulse width high 50 ns page mode characteristics chip erase waveforms t s = t h = 5 m sec (min.) t w = 10 msec (min.) v h = 12.0v 0.5v page mode write waveforms (1, 2) notes: 1. a6 through a12 must specify the same page address during each high to low transition of we (or ce). 2. oe must be high only when we and ce are both low. at28hc64b 2-273
software protected write cycle waveforms (1, 2) notes: 1. a6 through a12 must specify the same page address during each high to low transition of we (or ce) after the software code has been entered. 2. oe must be high only when we and ce are both low. load last byte to last address load data a0 to address 1555 load data 55 to address 0aaa load data aa to address 1555 notes for software program code: 1. data format: i/o7 - i/o0 (hex); address format: a12 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64-bytes of data are loaded. enter data protect state writes enabled (2) software data protection enable algorithm (1) load data xx to any address (4) load last byte to last address load data 55 to address 0aaa load data aa to address 1555 load data 80 to address 1555 load data 55 to address 0aaa load data aa to address 1555 load data 20 to address 1555 exit data protect state (3) software data protection disable algorithm (1) load data xx to any address (4) 2-274 at28hc64b
2. see ac read characteristics. symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns toggle bit characteristics (1) notes: 1. these parameters are characterized and not 100% tested. symbol parameter min typ max units t dh data hold time 0 ns t oeh oe hold time 0 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns data polling characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. toggle bit waveforms (1, 2, 3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used, but the address should not vary. data polling waveforms at28hc64b 2-275
2-276 at28hc64b
t acc (ns) i cc (ma) ordering code package operation range active standby 55 40 0.1 at28hc64b-55jc 32j commercial at28hc64b-55pc 28p6 (0 c to 70 c) at28hc64b-55sc 28s 70 40 0.1 at28hc64b-70jc 32j commercial at28hc64b-70pc 28p6 (0 c to 70 c) at28hc64b-70sc 28s at28hc64b-70tc 28t 40 0.1 at28hc64b-70ji 32j industrial at28hc64b-70pi 28p6 (-40 c to 85 c) at28hc64b-70si 28s at28hc64b-70ti 28t 90 40 0.1 at28hc64b-90jc 32j commercial at28hc64b-90pc 28p6 (0 c to 70 c) at28hc64b-90sc 28s at28hc64b-90tc 28t 40 0.1 at28hc64b-90ji 32j industrial at28hc64b-90pi 28p6 (-40 c to 85 c) at28hc64b-90si 28s at28hc64b-90ti 28t 120 40 0.1 at28hc64b-12jc 32j commercial at28hc64b-12pc 28p6 (0 c to 70 c) at28hc64b-12sc 28s at28hc64b-12tc 28t 40 0.1 at28hc64b-12ji 32j industrial at28hc64b-12pi 28p6 (-40 c to 85 c) at28hc64b-12si 28s AT28HC64B-12TI 28t note: 1. see valid part number table below. ordering information (1) at28hc64b 2-277
package type 32j 32 lead, plastic j-leaded chip carrier (plcc) 28p6 28 lead, 0.600" wide, plastic dual inline package (pdip) 28s 28 lead, 0.300" wide, plastic gull wing small outline (soic) 28t 28 lead, plastic thin small outline package (tsop) the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28hc64b 55 pc, sc at28hc64b 70 ji, pc, pi, sc, si, tc, ti at28hc64b 90 ji, pc, pi, sc, si, tc, ti at28hc64b 12 ji, pc, pi, sc, si, tc, ti valid part numbers 2-278 at28hc64b

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